Method for insulating a semiconductor material in a trench from a substrate

ABSTRACT

A semiconductor structure is disclosed. In one embodiment, the trench is formed in a substrate, including an upper portion and a lower portion, the upper portion including a lateral dimension larger than a lateral dimension of the lower portion. The lower portion is lined with a first insulating layer and is at least partially filled with a semiconductor material. The first insulating layer extends into the upper portion. A second insulating layer covers, at least partially, the substrate, a portion of the first insulating layer extending into the upper portion and the semiconducting material in the lower portion.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Utility patent application is a divisional application of U.S.application Ser. No. 11/781,582, filed Jul. 23, 2007, which isincorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a method for insulating asemiconducting material in a trench from a substrate by isotropicetching and by means of forming an insulating layer, and to a devicemanufactured by same, having self-aligned features.

Manufacturing methods are necessary for the production of highlyintegrated semiconductor devices, which offer a high accuracy in orderto fulfill the demanding production requirements. In order to reducepower loss during switching on operation of power semiconductor devices,i.e. trench transistors, the distance between neighboring devices shouldbe minimized. In doing so, the silicon region comprising the transistorchannel between the trenches is formed as small as possible. For thispurpose, self-adjusting methods can be used in order to place thesource/body contact of the transistor near to a trench and to stillensure a proper insulation between the source/body contact and the gatecontact in the trench. Reduction of any of these dimensions withoutcomplicating the process technology is difficult to achieve.

Thus, a new approach wherein, for example, insulating the trench and thesource/body contact and wherein the distance of the trench transistorscan be reduced and a self-adjusted contact between the trenches can beformed without increasing the process complexity is desirable.

BRIEF SUMMARY OF THE INVENTION

In accordance with embodiments, the present invention provides a methodfor insulating a semiconducting material in a trench from a substrate,the trench being formed in the substrate and comprising an upper portionand a lower portion, the lower portion being lined with a firstinsulating layer and filled at least partially with a semiconductingmaterial. The method comprises isotropic etching of the substrate andthe semiconductor material, forming a second insulating layer in thetrench, wherein the second insulating layer covers at least partiallythe substrate and the semiconducting material.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic cross-sectional view of a trench field-effecttransistor (FET) with a thermal-grown postoxide spacer.

FIG. 2 shows a raster electron microscope (REM) picture of a pluralityof trench FETs comprising the thermal-grown postoxide spacer.

FIGS. 3 a-c show the method for insulating a semiconducting material ina trench from a substrate in a sequence of drawings.

FIG. 4 shows another embodiment of forming a second insulating layer inthe trench.

FIG. 5 shows another embodiment of forming a second insulating layer inthe trench.

FIG. 6 shows another embodiment of forming a second insulating layer inthe trench.

FIG. 7 shows another embodiment of forming a second insulating layer inthe trench.

FIG. 8 shows another embodiment for the method for insulating asemiconductor material in a trench from a substrate with two trenches.

FIG. 9 shows a REM picture of the upper portion of a trench afterisotropic etching.

FIG. 10 shows an upper portion of a plurality of trenches afterisotropic etching.

FIG. 11 shows an upper portion of a trench after a longer isotropicetching.

FIG. 12 shows an upper portion of a plurality of trenches, after alonger isotropic etching.

FIG. 13 shows a self-adjusted contact between two trenches insulated bythe method for insulating a semiconducting material in a trench from asubstrate.

FIG. 14 shows another embodiment with a termination trench and a cellfield trench after polysilicon deposition for the gate electrode.

FIG. 15 shows a termination trench and the cell field trench afterisotropic etching.

DETAILED DESCRIPTION

With reference to the accompanying FIGS. 1 to 15, explanations andembodiments relating to the method for insulating a semiconductingmaterial in a trench from a substrate will be depicted in detail below.

FIG. 1 shows a schematic cross-sectional view of a silicon substrate 1comprising, two trenches, wherein a first trench is a cell field trench2 and a second trench is a termination trench 3. Both trenches 2,3comprise a lower portion 30 and an upper portion 40. The lower portion30 of the trenches 2, 3 comprise two semiconducting regions formed as agate electrode 10, comprising a double t-type shaped form, and anotherelectrode 11. The cell field trench 2 is formed as a vertical trenchmetal oxide semiconductor field effect transistor (MOSFET), with thegate electrode 10 and the insulating layer 15 forming the gate oxide inthe region of the gate electrode, the electrode 11, kept on a sourcepotential, a source region 90, formed on each side of the trench 2, achannel region 50 formed on each side of the trench 2 and a drain region7, formed by a substrate region. The termination trench 3 acts as acompletion trench for a plurality of cell field trenches and does notcomprise a working MOSFET structure.

The trenches 2,3 are lined with an insulating layer 15, which is alsoinsulating the gate electrode 10 against the electrode 11 within thetrenches. The upper portion 40 and the substrate 1 is covered by a thickthermal grown postoxide insulating layer 20. The postoxide layer 20 isforming a spacer and is insulating the gate electrode 10 and thesubstrate 1 against each other and against a subsequent deposition ofconducting material on top of the postoxide insulating layer 20. Thepostoxide insulating layer 20, respectively the postoxide spacer hasbeen formed in a high temperature process by transforming silicon at thesurface of the substrate 1 and at the surface of the semiconductingregion 10 in silicon oxide. Forming the postoxide insulating layer 20 ina high temperature step has some disadvantages for the operatingparameter of the trench MOSFET. Due to the high temperature, which isnecessary to form the postoxide insulating layer 20, a prior doping ofthe lower portion 30 of the trench MOSFET 2, in order to form the gateelectrode 10, can be affected such that the doping atoms diffuse in theadjacent channel region 50 of trench MOSFET. For this reason, theforming of the postoxide spacer can not be performed for a p-channeltrench MOSFET, whose gate electrode 10 has previously been realized by aboron implantation of the gate polysilicon material, forming the gateelectrode 10 and electrode 11. The boron might diffuse during theprocess of forming the postoxide insulating layer 20 in the channel 50of the trench MOSFET. This may lead to considerable fluctuations of thethreshold voltage Vth of the respective trench MOSFET. Furthermore, bothat n- and p-channel trench MOSFETs, the high temperature budget forforming the postoxide spacer may lead to a more intense diffusion of thedoping atoms out of the substrate. This may increase the fraction of thesubstrate 1 contributing to the switch-on resistance of the trenchMOSFET.

FIG. 2 shows a plurality of trenches 2, wherein the semiconductingmaterial 10 is insulated against the substrate 1 by the thermal-grownpostoxide spacer 20.

FIG. 3 c shows a schematic cross-sectional view of a trench 2 fabricatedwith the method for insulating a semiconducting material 10 in a trench2 against a substrate 1. The trench 2 is formed in the substrate 1,wherein the trench comprises an upper portion 40 and a lower portion 30,wherein the lower portion is lined with a first insulating layer 15 andfilled at least partially with the semiconducting material 10. The firstinsulating layer 15 comprises a portion 18 extending into the upperportion 40. The substrate 1 at the upper portion 40 is insulated by asecond insulating layer 25 from the semiconducting material 10 in thelower portion 30 of the trench 2.

FIGS. 3 a-3 c describe an embodiment of the method for insulating asemiconducting material 10 in a trench 2 from a substrate 1. Startingstructure of the method, shown in FIG. 3 a, is a trench 2 in a substrate1, wherein the trench 2 comprises an upper portion 40 and a lowerportion 30, wherein the lower portion 30 is lined with a firstinsulating layer 15 and filled at least partially with thesemiconducting material 10. The trench 2, as described above may beformed in different ways and may describe the state of a semiconductordevice at a certain production step. Furthermore, the described trenchmay be part of different semiconductor devices and, thereforemanufactured and processed in different ways. The trench 2 may be formedfor example, within the production process for a trench MOSFET, aninsulated gate bipolar transistor (IGBT), a Schottky-diode and such likesemiconductor devices. The substrate 1 and/or the semiconductingmaterial 10 can be identical and may, for example, comprise silicon,polysilicon, amorphous silicon, silicon carbide, gallium arsenide,indium phosphide or any other material which is used for producingsemiconductor devices. The semiconducting material 10 in the lowerportion 30 of the trench 2 can, for example, comprise polysilicon, whichcan be in-situ doped or doped in a consecutive implantation. Therefore,the semiconducting material 10 may comprise boron doping atoms for ap-type doping or, in the case of a n-type doping, arsenic, phosphorus orantimony doping atoms.

The first insulating layer 15, which lines the lower portion 30 of thetrench 2, can comprise, for example, silicon oxide, silicon nitride orany other insulating material used to fabricate a semiconductor device.The lower portion 30 of the trench 2 may, for example, comprise a walland a bottom and the above-mentioned first insulating layer 15 may onlyline the wall of the lower portion 30 of the trench 2. The lower portion30 of the trench 2 may comprise several structures, for example, twosemiconducting electrodes 10 and 11, as it is shown in FIG. 1, forfulfilling certain tasks in a semiconductor device.

As depicted in FIG. 3 b, the substrate 1 and the semiconducting material10 is isotropically etched 60 such that the lateral dimension of theupper portion 40 of the trench 2 is enlarged compared to the lateraldimension of the lower portion 30 of the trench 2. A spacer is formed bythe isotropic etching 60. The isotropic etching 60 of the substrate 1and the semiconducting material 10 does not, or almost not, etch thefirst insulating layer 15. As a consequence, a portion 18 of the firstinsulating layer 15 may extend into the upper portion 40.

The exact lateral dimension of the upper portion 40, respectively of thespacer and the portion 18 of the first insulating layer 15 extendinginto the upper portion 40 of the trench 2 depends on the precisecondition of the isotropic etching, the employed substrate material, thesemiconducting material and the employed first insulating material. Theetching process may depend on the etching medium, etching time, andetching factor, which the respective material comprises. The firstinsulating layer 15 should comprise a different etching selectivityagainst the used etching medium in order to be not, or almost notetched. The exact dimensions of the spacer and the portion 18 of thefirst insulating layer extending into the upper portion 40 can be tunedto the needs required to produce a certain semiconductor element ordevice. The etching can be performed with conventional means, forexample, with dry etching or wet etching, as it is employed in thesemiconductor process technology. In order to achieve isotropic etching,the substrate and the semiconducting material may be identical orcomprise a similar chemical composition. For producing a trench MOSFETthe substrate 1 may comprise silicon and the semiconducting material 10may, for example, comprise polysilicon doped with boron atoms in orderto form the gate electrode, and the first insulating layer 15 maycomprise silicon oxide. By isotropic etching the silicon substratedirectly after the definition and forming of the gate electrode in thesemiconducting material 10, a precise spacer may be formed withoutperforming any high temperature step, which could affect the doping ofthe gate electrode or the substrate. In modern silicon etching systems apitch of 100 nm with a variation smaller than 7 nm can be reached. Sincethe spacer is formed after the definition of the gate electrode withoutperforming any high temperature step, the described method offers thepossibility of realizing a boron doped gate electrode, in-situ-dopedrespectively implanted after the polysilicon deposition.

FIG. 3 c depicts the forming 70 of a second insulating layer 25 in thetrench 2, wherein the second insulating layer 25 covers at leastpartially the substrate 1 in the upper portion and the semiconductingmaterial 10.

The second insulating layer 25 can comprise an identical material likethe first insulating layer 15. The second insulating layer may, forexample, comprise at least one of the consecutive materials: Siliconoxide, silicon nitride, phosphorus silicate glass, boron phosphorussilicate glass, polymeric or organic material. Forming the secondinsulating layer 25 can be done in a conventional way, which isappropriate for the respective semiconductor process technology.

The second insulating layer 25 can be formed in different ways. FIG. 4shows, for example, a completely filled upper portion 40 of the trench2, with the second insulating layer 25. FIG. 5 depicts anotherembodiment, wherein the upper portion 40 is almost completely filled, upto the substrate surface 1′, with the insulating layer 25.

Forming the second insulating layer 25 can be an interlevel dielectric(ILD) filling with respective materials. This can be done, for example,by using a mask or, as it is shown in FIG. 6, in such a way that thesecond insulating layer 25 covers at least partially the surface 1′ ofthe substrate.

The second insulating layer 25 in the trench may be formed such thatonly a part of the semiconducting material 10 and the adjacent substrate1 in the upper portion 40 of the trench 2 is insulated (see FIG. 7). Theforming of the second insulating layer in the trench may be performedsuch that the sidewalls of the upper portion are at least partiallycovered as well as the semiconducting material 10.

FIG. 8 shows another embodiment of the present invention, wherein thesubstrate 1 comprises a further structure. In FIG. 8, for example, asecond trench 2′, with an upper portion 40′, a lower portion 30′, asemiconducting material 10′, a first insulating layer 15′, a secondinsulating layer 25′ and a portion 18′ of the first insulating layerextending into the upper portion 40′ of the trench 2′. Both trenches 2and 2′ are identical and fabricated according to the above-mentionedmethod for insulating a semiconducting material in a trench from asubstrate. The distance D between both trenches 2, 2′, respectively D′as it is indicated in FIG. 8 with dotted lines, can be controlled by theabove-mentioned isotropic etching 60. For example, the dotted lines forthe upper portion 40, 40′ refer to a longer isotropic etching 60 andtherefore to a smaller distance D′ between the trenches 2 and the 2′.This means that the distance between the trenches can be easily andprecisely controlled. It is also possible to control the distance Dagainst a further structure, which is here not described in detail,instead against a second trench 2′.

The REM pictures in FIGS. 9 and 10 show, in more detail, the situationafter isotropic etching one trench (FIG. 9) and a plurality of trenches(FIG. 10). The lateral dimension of the upper portion 40 in FIG. 9 is,in this case, on each sidewall of the trench enlarged by 50 nm to 55 nm.The semiconducting material 10 in the lower portion 30 of the trench isapproximately 80 nm ablated. The portion 18 of the first insulatinglayer 15, extending into the upper portion 40, is formed, in contrast tothe schematic figures (for example FIG. 7), in a way where the abrasiveon both sides of the insulating layer 15 may not be equal. By isotropicetching, the schematic depicted spacer 65 can be formed at the sidewallof the upper portion 40 of the trench, as it is schematically shown inFIG. 9.

FIGS. 11 and 12 depict the same structures as in FIGS. 9 and 10, butwith a longer isotropic etching time, leading to a further enlargementof the lateral dimension of the upper portion 40, in this case, atapproximately 80 nm on each sidewall of the trench and a verticalabrasive in the trench at about 140 nm.

FIGS. 9 to 12 show that the isotropic etching can be precisely performedand, therefore, the width of the spacer and the distance between furtherstructures, in this case further trenches, can be adjusted to therespective needs of the semiconductor device.

FIG. 13 shows two trenches 2, 2′ in a certain distance adjusted byisotropic etching. Both trenches are filled with the second insulatinglayer 25, 25′ in the upper portion 40, 40′. After forming the secondinsulating layer in the trenches, a contact hole 75 between the twosecond insulating layers 25, 25′, respectively the spacers formedtherewith may be formed by means of conventional etching. Afterwards,the contact hole 75 can be filled or covered with a conducting material80 in order to form a contact to, or an electrode in the substrate 1between the two trenches 2 and 2′. It should be mentioned that, forexample in the case of the trench MOSFET, the upper fraction 90 of thesubstrate 1 between the trenches may be formed as a source region and,therefore, a source contact is formed in the region 90 and a lowerfraction of the substrate 1 may be formed as a body contact in a bodyregion 100. Depending on the way as to how the forming of the secondinsulating layer was performed and as to whether the surface 1′ of thesubstrate was covered with the second insulating layer 25, it might benecessary to first remove the second insulating layer 25 down to thesurface 1′ of the substrate before etching the contact hole 75 andforming the contact with conducting material 80. If necessary, theremoval of the second insulating layer 25 may be done by conventionalmeans of etching, polishing or smoothing. For a proper function of thetrench MOSFET, it may be important that the distance D between thetrenches and the contact can be precisely adjusted. This can be achievedwith the above-explained method for insulating a semiconducting materialin a trench from a substrate, by forming a self-adjusted contact betweentwo trench MOSFET. Self-adjusted means that no further mask step isneeded to define the contact hole. This can be achieved by a properisotropic etching 60 and a forming a proper second insulating layer 25.It is clear, that the forming of the contact hole and the forming of thecontact can be done in parallel for a plurality of trenches, as it isindicated by FIGS. 10 and 12 showing a plurality of trenches inparallel.

FIGS. 14 and 15 show a termination trench 3 and a cell field trench 2.In FIG. 14 both trenches and the surface of the substrate 1 are linedwith a first insulating layer 15, wherein the insulating layer 15 isthicker at the upper portion of the termination trench 3. Furthermoreboth trenches 2,3 comprise a semiconducting region 11 insulated from asemiconducting region 10. FIG. 14 shows both trenches 2,3 after thedeposition of polysilicon 12 in order to form the gate electrode 10 inthe cell field trench 2. The polysilicon gate material 12 can be in-situboron doped or doped by a following implantation of doping atoms. Theexcess polysilicon gate material 12 at the top of the trenches 2,3 canbe removed by means of conventional polysilicon photolithographytechniques and a subsequent polysilicon gate material 12 recess etching.After removing the excess polysilicon gate material 12, some firstinsulating layer 15 a might be left on the sidewalls of the upperportion 40 of the trenches 2,3 and on the top of the cell field trench2. This residual oxide may be removed by conventional means of etching,such that the starting trench of the method for insulating asemiconducting material in a trench from a substrate, as it is shown inFIG. 3 a can be created. It should be noted that there are differentways for forming the above-mentioned starting trench.

FIG. 15 depicts a situation after performing the isotropic etching tothe termination trench 3 and the cell field trench 2. The upper portionof the termination trench 3 is still protected with a first insulatinglayer 15 and, therefore, the substrate 1 adjacent to the upper portionof the termination trench may be not removed. In contrast, in the upperportion 40 of the cell field trench 2 the above-mentioned spacer can beformed. The isotropic silicon etching can be done for a certain time inorder to reach a certain adjustment of the spacer. After the isotropicetching, an interlevel dielectric filling may be performed and, ifnecessary, a subsequent oxide recess step to remove the excess oxidefrom the interlevel dielectric filling on top of the surface of thesubstrate. In a consecutive step, a self-adjusted contact hole may nowbe etched between two trenches and filled with a conducting material.

In the case of a trench MOSFET, a contact to the above-mentioned sourceand bulk region in the substrate between two trenches, may be formedthereby. By isotropic etching and forming a second insulating layer aspacer can be formed between the trenches and the source/body contact.This way to form the spacer and the self-adjusted contact hole may avoidthe high temperature step to form a thermal-grown postoxide insulatinglayer and, as a consequence, allow an in-situ p-doping of the gateelectrode, without to cause a significant larger variation in thedistance between the trenches and the source/body contacts.

The above-mentioned invention is not only restricted to trench MOSFETs,but can also be employed with other semiconductor structures andsemiconductor devices to form, for example, a self-adjusted contacthole, an insulator between a semiconducting material in a trench and asubstrate, respectively a spacer.

The electrode 11 in the lower portion of the trench, for example, inFIGS. 14 and 15 may be formed as a field plate, which may kept at thesame potential as the source of the trench MOSFET. The channel of thetrench MOSFET can be formed radical adjacent to the lower portion of thetrench, wherein, for example, the drain region might be formed in alower portion of the substrate. The substrate may be n- or p-dopeddepending on the MOSFET being formed. The substrate may comprisedifferent zones, with a different doping concentration in order to form,for example, a source region, which can then be contacted via a contacthole between two trenches, formed with the method described above.

1. A semiconductor structure comprising: a trench being formed in asubstrate, comprising an upper portion and a lower portion, the upperportion comprising a lateral dimension larger than a lateral dimensionof the lower portion, wherein the lower portion is lined with a firstinsulating layer and is at least partially filled with a semiconductormaterial, the first insulating layer extending into the upper portion;and a second insulating layer covering, at least partially, thesubstrate, a portion of the first insulating layer extending into theupper portion and the semiconducting material in the lower portion.
 2. Asemiconductor device comprising: a trench being formed in the substrate,comprising an upper portion and a lower portion, the upper portioncomprising a lateral dimension larger than a lateral dimension of thelower portion, wherein the lower portion is lined with a firstinsulating layer and, at least partially, filled with a semiconductingmaterial, forming an at least first electrode, the first insulatinglayer extending into the upper portion; a second insulating layercovering, at least partially, the substrate, the portion of the firstinsulating layer extending into the upper portion and the semiconductingmaterial in the lower portion; and an at least second electrode in thesubstrate.
 3. The semiconductor device as claimed in claim 2, whereinthe second insulating layer covers, at least partially, the sidewalls ofthe upper portion and the semiconducting material, forming an at leastfirst electrode.
 4. The semiconductor device as claimed in claim 2,wherein the upper portion of the trench is filled with a secondinsulating layer.
 5. The semiconductor device as claimed in claim 2,wherein the lower portion comprises a wall and a bottom and the firstinsulating layer lines the wall of the lower portion.
 6. Thesemiconductor device as claimed in claim 2, wherein the substratecomprises a second trench laterally shifted to the trench, and wherein acontact hole filled with contacting material between the trench and thesecond trench forms a contact to the at least second electrode.